Researchers from a National Institute of Standards and Technology (NIST) and Intel reported success regulating an X-ray pinch technique to accurately magnitude comforts on a silicon chip to within fractions of a nanometer, or about a breadth of a singular silicon atom.
The feat could make a initial record famous as CDSAXS (critical-dimension tiny angle X-ray scattering) a tip contender in a competition to rise new in-line routine control collection for measuring vanishingly tiny comforts on next-generation mechanism chips.
“The semiconductor attention is regulating out of measure methods that work non-destructively on their ever-smaller next-generation nanostructures,” says NIST materials scientist R. Joseph Kline. “These are by distant a smallest and many formidable done nanostructures characterized by CDSAXS. The formula uncover that CDSAXS has a fortitude to accommodate next-generation metrology requirements.”
With a stretch of lines, trenches, holes and other comforts on silicon slices timorous to single-digit nanometers, measure collection prolonged used to guard chip prolongation are coming their limits. Factor in a flourishing complexity of chip design—such as building stack-like transistors instead of prosaic ones, a change begun with Intel’s introduction of FinFET transistors in 2011—and it’s easy to know because semiconductor manufacturers are fervent for softened measure capabilities.
The NIST and Intel researchers used CDSAXS to magnitude measure on silicon wafers built during Intel’s investigate comforts with a periodic array of uneven lines. The array was done by representation quartering, a routine that quadruples a series of interconnect lines in a space that routinely would accommodate usually one. The perplexing arrays of lines were done regulating mixed patterning stairs chip makers now contingency occupy to emanate comforts over a capabilities of existent light-based copy equipment. Throughout, removing accurate measurements is critical; misalignments during a consecutive patterning routine can outcome in systematic errors, or flaws, in a chip.
A smirch of sold concern—and a concentration of a NIST-Intel study—is representation error, variations in a stretch from one line corner to a next.
“The semiconductor attention has not usually decreased product dimensions, though we’ve also grown increasingly formidable 3D structures. These structures are apropos really formidable to impersonate non-destructively with compulsory in-line SEM [scanning nucleus microscope],” pronounced Scott List, principal operative in Intel’s Components Research Group. “Early formula of NIST’s state-of-the-art CDSAXS measurements of these nanometer-sized structures have supposing really useful atomic scale fortitude of their 3D profiles.”
In a custom-made representation scrutinized in a study, lines imitative shark fins were 12 nanometers wide. The space between lines sundry ever so slightly—by reduction than 0.5 nanometer—from a representation of 32 nanometers.
CDSAXS measurements of periodic representation errors—deviations from 32 nanometers—were accurate to within 0.1 nanometer; and measurements of line shapes were accurate to about 0.2 nanometer.
Since 2000, NIST has been pioneering a focus of small-angle X-ray pinch to accommodate a ever-more perfectionist measure needs of a semiconductor industry, which, for decades, has been doubling a firmness of transistors on a chip about each dual years in suitability with Moore’s Law. Today’s leading-edge integrated circuits fist several billion transistors on a cut of silicon smaller than a standard postage stamp.
Currently used dimensional metrology collection rest on manifest and ultraviolet light with wavelengths most incomparable than a comforts being measured. The X-rays used in CDSAXS have a wavelength reduction than 0.1 nanometer, most smaller than a measure of comforts on destiny generations of mechanism chips. CDSAXS exploits a brief wavelength of X-rays and their attraction to incompatible densities of electrons in a materials they strike.
The noncontact, non-destructive technique does not need any representation preparation, and it works with exam structures already used by semiconductor makers. CDSAXS, however, does not produce a homogeneous of an X-ray design of, for example, a damaged wrist. Rather, patterns of X-rays sparse by electrons in a nanostructure are prisoner by a detector, providing information to be crunched by computers to solve for a strange shape.
The analyses review a settlement of sparse X-rays to delicately grown figure models of arrays of nanostructured comforts on a surface. This data-fitting procession might go by several million rounds before achieving a acceptable compare between unnatural and totalled patterns of nucleus densities.
Following other studies demonstrating a capabilities of CDSAXS for a horde of nanoscale measurements, a NIST-Intel investigate on formidable samples deputy of next-generation semiconductor production shows that CDSAXS can broach a preferred dimensional resolution.
The formula should yield serve procedure for ongoing efforts to rise compress sources of X-rays with a power compulsory for in-line CDSAXS in semiconductor production facilities. The NIST-Intel, proof-of-concept investigate was conducted during a Advanced Photon Source (APS) during Argonne National Laboratory, that measures 1,104 meters in circumference—more than 12 football fields around—and accommodates some-more than 60 experiments during one time. Previous CDSAXS studies were conducted during APS or identical initial facilities, famous as synchrotron light sources.